1. Field of the Invention
This invention relates to a semiconductor integrated circuit device having a test mode setting circuit.
2. Description of the Related Art
Setting of a test mode in a semiconductor integrated circuit device, for example, a semiconductor memory device is effected by supplying a test signal when a voltage ("HH" level=approx. 12 V) higher than a normal input level (0 to 5 V) is applied to a pin which has no connection to the test, for example, an address pin. This type of test mode setting circuit is described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. SC-22, NO. 5, OCTOBER 1987 pp. 669-675 OHTSUKA et al.; A 4-Mbit CMOS EPROM, for example.
FIG. 1 shows the conventional test mode setting circuit described above and the peripheral circuit portion thereof in the semiconductor memory device. As shown in FIG. 1, an address signal Add input to an address input pad 10 is supplied to an address buffer 11 and a high potential detection circuit 12 acting as a test mode setting circuit. Internal address signals Ai, Ai are supplied from the address buffer 11 to a decoder (not shown) and a test signal TSi for switching the semiconductor memory device into the test mode is output from the high potential detection circuit 12.
The address buffer 11 includes P-channel MOS transistors 13, 14, N-channel MOS transistors 15, 16 and inverters 17 to 20. The current paths of the MOS transistors 13, 14, 15 are connected in series between the power sources Vcc and Vss. The current path of the MOS transistor 16 is connected between a common connection node of the MOS transistors 14 and 15 and the ground node Vss. A chip enable signal CE is supplied to the gates of the MOS transistors 13, 16. The gates of the MOS transistors 14, 15 are connected to the address input pad 10. The input terminal of the inverter 17 is connected to the drain common connection node of the MOS transistors 14, 15, 16 and the output terminal thereof is connected to the input terminal of the inverter 18. The input terminal of the inverter 19 is connected to the output terminal of the inverter 18 and an internal address signal Ai is output from the output terminal thereof. Further, the input terminal of the inverter 20 is connected to the output terminal of the inverter 19 and an internal address signal Ai is output from the output terminal thereof.
The high potential detection circuit 12 includes P-channel MOS transistors 21, 22, N-channel MOS transistor 23 and inverters 24 and 25. The source of the MOS transistor 21 is connected to the address input pad 10 and the gate and drain thereof are connected to the source of the MOS transistor 22. The gate of the MOS transistor 22 is applied with the power source voltage Vcc and the drain thereof is connected to the drain of the MOS transistor 23. The gate of the MOS transistor 23 is applied with the power source voltage Vcc and the source thereof is connected to the ground node Vss. The input terminal of the inverter 24 is connected to a drain common connection node of the MOS transistors 22, 23 and the output terminal thereof is connected to the input terminal of the inverter 25. A test signal TSi for switching the semiconductor memory device into the test mode is output from the output terminal of inverter 25.
With the above construction, since the MOS transistor 13 is set in the OFF state and the MOS transistor 16 is set in the ON state when the chip enable signal CE is set at the "H" level, the input terminal of the inverter 17 is set to the "L" level. As a result, the internal address signal Ai is fixed at the "H" level and the internal address signal Ai is fixed at the "L" level.
When the chip enable signal CE is inverted to the "L" level, the MOS transistor 13 is set into the ON state, the MOS transistor 16 is set into the OFF state, and the address signal Add supplied to the address input pad 10 is inverted by a CMOS inverter constructed by the MOS transistors 14 and 15 and then supplied to the input terminal of the inverter 17. As a result, the internal address signal Ai becomes a signal which is in phase with the address signal Add supplied externally, the internal address signal Ai becomes a signal which has an inverted phase with respect to the address signal Add, and the internal address signals Ai, Ai are supplied to a row decoder or column decoder.
When a potential applied to the address input pad 10 is set at the level (for example, 0 to 5 V) of the address signal Add, the MOS transistor 22 is set in the OFF state, the MOS transistor 23 is set in the ON state and the test signal TSi output from the inverter 25 is kept at the "L" level in the high potential detection circuit. On the other hand, when a potential of "HH" level is applied to the address input pad 10, the MOS transistors 21, 22 are set into the ON state and the MOS transistor 23 is set into the OFF state, and therefore, the input terminal of the inverter 24 is set to the "H" level. As a result, the test signal TSi output from the inverter 25 is set to the "H" level so as to set the test mode.
The test mode setting circuit constructed by the high potential detection circuit has an advantage that the test can be effected even after the chip is sealed into the package and an increase in the number of pins can be suppressed and is widely used.
Now, suppose the case of gate disturb test in a non-volatile semiconductor memory device (such as EPROM, flash EEPROM) as an example of a case wherein the above test mode setting circuit is used. Since all of the word lines are set in the selected state irrespective of an input address in the gate disturb test, one address input pin for the row address can be used as a test mode setting pin for inputting the "HH" level.
However, in the test such as the test mode for the sense amplifiers, for example, in which it is necessary to input all of the control signals and all of the address signals, a problem that the test mode setting pin cannot be defined occurs. Further, since the number of pins is limited, the number of test modes effected with the chip sealed in the package is limited. For example, it is further difficult to effect the test having a combination of a large number of test items such as changing or switching of part of the settings of the power source circuit and application of the same stress as that to the word line to another transistor (for example, Y selector) in the gate disturb test.
Further, when the test is effected, it is necessary to generate a high voltage signal of 12 V. However, since the IC tester does not have many terminals capable of generating such a high voltage, it becomes necessary to take a lot of labor and time for preparing the test.
Particularly, in the semiconductor memory device having the conventional test mode setting circuit as shown in FIG. 1, the types, the combinations and the number of tests which can be effected are limited, and therefore, the possibility of interference with the development and the analysis for defects becomes high.